Conventional memory devices are limited to mostly 1 bit at the intersection of a wordline (WL) and a bitline (BL) in a memory array. For example, DRAM devices are limited to 1 bit per intersection, which corresponds to the presence of only one capacitor at each node. Similarly, FLASH devices have at most 2 bits per cell, in a multibit or multilevel configuration. These 2 bits can be detected based on the magnitude and direction of the current flow across the cell.
However, conventional memory devices are not capable of easily accommodating more than two memory bits at every crosspoint intersection. It would therefore be desirable to expand the access capability in memory devices to select or read multiple bits at every memory area or crosspoint that is normally desired by one memory wordline and bitline.
One problem facing conventional semiconductor lithographic techniques is the ability to electrically interconnect nano-scaled lines or patterns (on the order of 1 nm to 100 nm) and micro-scaled lines or patterns (on the order of 90 nm or a feature that could be typically defined by semiconductor processes such as lithography). Such connection is not currently practical, as it requires a significant interconnect semiconductor area, which increases the cost and complexity of the manufacturing process or the final product.
It would therefore be desirable to have a multiplexing device or an addressing device that establishes selective contact to memory cells, logic devices, sensors, or between nano-scaled lines and micro-scaled lines within a minimal space, thus limiting the overall cost and complexity of the final product.
The need for such memory cells, logic devices, sensors, and other similar addressable devices has heretofore remained unsatisfied.